Dynamic redundancy identification in automatic test generationABRAMOVICI, M; MILLER, D. T; ROY, R. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 3, pp 404-407, issn 0278-0070Article

Fault simulation and test generation in combinational circuits using atomic digraphsVILLAR, E; BRACHO, S.International journal of electronics. 1985, Vol 59, Num 4, pp 461-470, issn 0020-7217Article

Design of totally self-checking checker for 1-out-of-3 codeGOLAN, P.IEEE transactions on computers. 1984, Vol 33, Num 3, issn 0018-9340, 285Article

Zur schnellen Fehlersimulation in kombinatorischen Schaltungen = Sur l'accélération de la simulation des fautes dans les circuits combinatoires = On the acceleration of fault simulation in combinational circuitsANTREICH, K. J; SCHULZ, M. H.AEU. Archiv für Elektronik und Übertragungstechnik. 1986, Vol 40, Num 6, pp 355-362, issn 0001-1096Article

Processus dynamiques dans les automates à actions périodiquesLEVIN, V. I.Izvestiâ Akademii nauk SSSR. Tehničeskaâ kibernetika. 1986, Num 1, pp 81-93, issn 0002-3388Article

Propriétés des pannes du type «court-circuit» dans les circuits combinatoiresSAPOZHNIKOV, V. V; SAPOZHNIKOV, V. V; SAPOZHNIKOV, V. V; SAPOZHNIKOV, V. V; CHUKHONIN, V. M et al.Avtomatika i telemehanika. 1984, Num 3, pp 142-150, issn 0005-2310Article

Fault tolerant circuit using alternate-data retry strategyHASEGAWA, Y; NAITO, S.Systems, computers, controls. 1983, Vol 14, Num 1, pp 86-94, issn 0096-8765Article

Testability measures in pseudorandom testingERCOLANI, S; FAVALLI, M; DAMIANI, M et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 6, pp 794-800, issn 0278-0070Article

On the complexity of estimating the size of a test setBALAKRISHNAN KRISHNAMURTHY; AKERS, S. B.IEEE transactions on computers. 1984, Vol 33, Num 8, pp 750-753, issn 0018-9340Article

A simple random test procedure for detection of single intermittent fault in combinational circuitsVIRUPAKSHIA, A. R; PRATAPA REDDY, V. C. V.IEEE transactions on computers. 1983, Vol 32, Num 6, pp 594-597, issn 0018-9340Article

Good controllability and observability do not guarantee good testabilitySAVIR, J.IEEE transactions on computers. 1983, Vol 32, Num 12, pp 1198-1200, issn 0018-9340Article

An efficient delay test generation system for combinational logic circuitsEUN SEI PARK; MERCER, M. R.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 7, pp 926-938, issn 0278-0070Article

Sur les circuits combinatoires pour le diagnostic fonctionnel et de test des dispositifs discretsSPERANSKIJ, D. V.Avtomatika i telemehanika. 1985, Num 1, pp 122-126, issn 0005-2310Article

Reliability evaluation of logic circuitsROCA, J. L.Microelectronics and reliability. 1985, Vol 25, Num 2, pp 257-260, issn 0026-2714Article

On properties of algebraic transformations and the synthesis of multifault-irredundant circuitsHACHTEL, G; JACOBY, R. M; KEUTZER, K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 3, pp 313-321, issn 0278-0070Article

Modelling digital circuits with delays by Stochastic Petri NetsCASTAGNOLO, B; CORSI, F.Microelectronics and reliability. 1983, Vol 23, Num 6, pp 1075-1086, issn 0026-2714Article

Synthèse des circuits combinatoires faciles à tester pour les pannes du type court-circuitGORYASHKO, A. P.Izvestiâ Akademii nauk SSSR. Tehničeskaâ kibernetika. 1983, Num 5, pp 70-76, issn 0002-3388Article

Une méthode structurale pour déterminer les relations entre les pannes dans les circuits numériques combinatoiresVASHIN, V. A.Avtomatika i telemehanika. 1983, Num 12, pp 103-114, issn 0005-2310Article

Pseudorandom testingWAGNER, K. D; CHIN, C. K; MCCLUSKEY, E. J et al.IEEE transactions on computers. 1987, Vol 36, Num 3, pp 332-343, issn 0018-9340Article

An efficient algorithm for single and multiple fault test sets generationSAILENDRANATH BANERJEE; RANAJITKISHORE THAKUR; PRAMODE RANJAN BHATTACHARJEE et al.International journal of computer mathematics. 1985, Vol 18, Num 2, pp 121-133, issn 0020-7160Article

Autocorrelation testing of combinational circuitsABORHEY, S.IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 1, pp 57-61, issn 0143-7062, 5 p.Article

Algorithme de recherche libre des défauts multiples dans les dispositifs combinatoiresKISELEV, V. V; KON, E. L.Avtomatika i telemehanika. 1984, Num 11, pp 155-163, issn 0005-2310Article

Universal tests for detection of input/output stuck-at and bridging faultsKARPOVSKY, M.IEEE transactions on computers. 1983, Vol 32, Num 12, pp 1194-1198, issn 0018-9340Article

Synthèse des tests de contrôle des circuits combinatoires arborescentsAJRAPETYAN, A. N.Izvestiâ Akademii nauk SSSR. Tehničeskaâ kibernetika. 1983, Num 5, pp 77-84, issn 0002-3388Article

ZUR ALGEBRAISCHEN BESTIMMUNG VON SIGNAL-NEBENBEDINGUNGEN IN KOMBINATORISCHEN NETZWERKEN. = DETERMINATION ALGEBRIQUE DES CONDITIONS SECONDAIRES DE SIGNAL DANS LES RESEAUX COMBINATOIRESLEHMANN K; FUGERT E.1976; NACHR.-TECH., ELEKTRON.; DTSCH.; DA. 1976; VOL. 26; NO 4; PP. 146-149; BIBL. 4 REF.Article